Differential receivers that support standards such as low voltage differential signaling (LVDS), Sub-LVDS, scalable low voltage signaling (SLVS), differential high-speed transceiver logic (DIFF_HSTL) and differential stub speed terminated logic (DIFF_HSTL) are powered by a 1.8V supply which is sufficient to handle input common mode voltage from 1.425V to 0V. However, as the supply voltages in ICs continues to decrease, the operation of certain transistors may be affected. For example, in a conventional receiver device such as a folded cascade structure where the supply voltage is very low, there may not be enough headroom to keep the devices in saturation. As a result, there is higher variation in current and duty cycle/performance. Because a folded cascade structure is a high gain structure, even a small offset in the differential input may result in high skew. Further, a folded cascade structure may not support higher common mode voltages, which may be as high as the supply voltage. With efforts to reduce Vccaux_IO supply voltages below 1.8V to 1.5V for example, these existing problems will be further aggravated.
Accordingly, circuits and methods that enable the shifting of a common mode voltage to accommodate different common mode voltages in integrated circuit devices would be beneficial.